The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2010

Filed:

Jun. 12, 2006
Applicants:

Marcos K. Aguilera, Palo Alto, CA (US);

Christos Karamanolis, Palo Alto, CA (US);

Arif Merchant, Palo Alto, CA (US);

Mehul A. Shah, Palo Alto, CA (US);

Alistair Veitch, Palo Alto, CA (US);

Inventors:

Marcos K. Aguilera, Palo Alto, CA (US);

Christos Karamanolis, Palo Alto, CA (US);

Arif Merchant, Palo Alto, CA (US);

Mehul A. Shah, Palo Alto, CA (US);

Alistair Veitch, Palo Alto, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 15/167 (2006.01);
U.S. Cl.
CPC ...
Abstract

A transactional shared memory system has a plurality of discrete application nodes; a plurality of discrete memory nodes; a network interconnecting the application nodes and the memory nodes, and a controller for directing transactions in a distributed system utilizing the shared memory. The memory nodes collectively provide an address space of shared memory that is provided to the application nodes via the network. The controller has instructions to transfer a batched transaction instruction set from an application node to at least one memory node. This instruction set includes one or more write, compare and read instruction subsets, and/or combinations thereof. At least one subset has a valid non null memory node identifier and memory address range. The memory node identifier may be indicated by the memory address range. The controller controls the memory node responsive to receipt of the batched transaction instruction set, to safeguard the associated memory address range during execution of the transaction instruction set. The batched transaction instruction set is collectively executed atomically. A notification instruction set may also be used to establish a notification, triggered upon a subsequent write event upon at least a portion of a specified address range.


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