The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2010

Filed:

Aug. 14, 2008
Applicants:

Priscilla E. Escobar-bowser, Plano, TX (US);

Indumini Ranmuthu, Plano, TX (US);

Inventors:

Priscilla E. Escobar-Bowser, Plano, TX (US);

Indumini Ranmuthu, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0175 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit () includes a translator circuit () for translating from a lower logic-level voltage range signal ((),()) to a higher logic-level voltage range signal ((),()). The translator () includes a differential input stage () including a first (Q) and a second input transistor (Q) coupled to receive at least a first input signal ((),()) that defines the lower voltage range signal. A voltage followerincludes first and second follower transistors (Q, Q). An output of the first and second input transistors (Q, Q) is coupled to inputs of the first and second follower transistors (Q, Q). A dynamic gain boosting switching circuit () is coupled to receive outputs from the first and second follower transistors (Q, Q) and includes a first and a second control node (). The switching circuit () include a first positive feedback loop including a first internal feedback transistor (MN) that reinforces a signal level at the first control node () and a second positive feedback loop including a second internal feedback transistor (MN) that reinforces a signal level at the second control node. An output stage () has at least one input coupled to receive at least one output signal from the switching circuit () and provide at least one translated output supplying the higher logic-level voltage range signal.


Find Patent Forward Citations

Loading…