The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2010

Filed:

Nov. 30, 2005
Applicants:

Chong-man Yun, Seoul, KR;

Kwang-hoon OH, Seoul, KR;

Kyu-hyun Lee, Bucheon-si, KR;

Young-chull Kim, Incheon Meropolitan, KR;

Inventors:

Chong-man Yun, Seoul, KR;

Kwang-hoon Oh, Seoul, KR;

Kyu-hyun Lee, Bucheon-si, KR;

Young-chull Kim, Incheon Meropolitan, KR;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/58 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided are a power semiconductor device using a silicon substrate as a FS layer and a method of manufacturing the same. A semiconductor substrate of a first conductivity type is prepared. An epitaxial layer is grown on one surface of the semiconductor substrate. Here, the epitaxial layer is doped at a concentration lower than that of the semiconductor substrate and is intended to be used as a drift region. A base region of a second conductivity type is formed in a predetermined region of the epitaxial layer. An emitter region of the first conductivity type is formed in a predetermined region of the base region. A gate electrode with a gate insulating layer is formed on the base region between the emitter region and the drift region of the epitaxial layer. A rear surface of the semiconductor substrate is ground to reduce the thickness of the semiconductor substrate, thereby setting an FS region of the first conductivity type. A collector region of the second conductivity type is formed on the ground surface of the semiconductor substrate of the FS region, thereby forming an FS-IGBT.


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