The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2010

Filed:

Jan. 17, 2007
Applicants:

Michael Chan, Ontario, CA;

Paul Leventis, Ontario, CA;

David Lewis, Ontario, CA;

Ketan Zaveri, San Jose, CA (US);

Hyun MO Yi, Mountain View, CA (US);

Chris Lane, San Jose, CA (US);

Inventors:

Michael Chan, Ontario, CA;

Paul Leventis, Ontario, CA;

David Lewis, Ontario, CA;

Ketan Zaveri, San Jose, CA (US);

Hyun Mo Yi, Mountain View, CA (US);

Chris Lane, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

An embodiment of the present invention provides a programmable logic device ('PLD') including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs for determining routing selections. Other embodiments provide proximate grouping of vertical lines driven from a same row. Other embodiments provide definition of spare row locations once defective row locations are known.


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