The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2010

Filed:

Dec. 23, 2002
Applicants:

Seung Kyu Choi, Daegu, KR;

Kwang Soon Park, Daegu, KR;

Chul Woo Im, Kumi-shi, KR;

Sang Moo Song, Daegu, KR;

Choel Min Woo, Sangju-shi, KR;

Inventors:

Seung Kyu Choi, Daegu, KR;

Kwang Soon Park, Daegu, KR;

Chul Woo Im, Kumi-shi, KR;

Sang Moo Song, Daegu, KR;

Choel Min Woo, Sangju-shi, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1345 (2006.01);
U.S. Cl.
CPC ...
Abstract

A line-on-glass (LOG) type liquid crystal display device prevents deterioration in picture quality due to line resistances in LOG signal lines includes a display area having liquid crystal cells arranged at crossings of gate and data lines, a storage capacitor arranged within each of the liquid crystal cells for maintaining charged pixel voltages, and a dummy gate line. A line-on-glass type signal line group outside the display area transmits driving signals to the gate driver integrated circuits for driving the gate lines. A first signal line outside the display area is mounted on gate tape carrier packages. A second signal line connects the first gate low voltage and dummy lines, is insulated from, and crosses the gate lines outside the display area. A third signal line connects the first gate low voltage line and the dummy gate line to connect the first and second gate low voltage lines in parallel.


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