The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 05, 2010
Filed:
Sep. 06, 2007
Kerry Bernstein, Underhill, VT (US);
Philip G. Emma, Danbury, CT (US);
John A. Fifield, Underhill, VT (US);
Paul D. Kartschoke, Williston, VT (US);
William A. Klaasen, Underhill, VT (US);
Norman J. Rohrer, Underhill, VT (US);
Kerry Bernstein, Underhill, VT (US);
Philip G. Emma, Danbury, CT (US);
John A. Fifield, Underhill, VT (US);
Paul D. Kartschoke, Williston, VT (US);
William A. Klaasen, Underhill, VT (US);
Norman J. Rohrer, Underhill, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors. Also, there is provided a design structure embodied in a machine readable medium used in a design process, and which includes such error correcting logic system.