The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2010

Filed:

Apr. 05, 2004
Applicant:

Steven E. Strauss, Orefield, PA (US);

Inventor:

Steven E. Strauss, Orefield, PA (US);

Assignee:

Agere Systems Inc., Allentown, PA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02J 1/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The effects of power supply resistance and internal resistance drop are measured at any time in the interior or other strategic areas of an IC device during steady-state operation, and the results of managed internal voltage regulation are fed back from at least one point, but preferably from several or more points throughout the power grid of the IC. Thus, stability of voltage regulation on an IC including at least one integrated voltage regulator is dynamically controlled with voltage regulation that is managed to effectively provide a 'secondary' voltage regulation of the output of one or more voltage regulators to provide a desired voltage output result on one or more portions of a power grid. The management may be implemented in an IC having a singular power grid with respect to a particular supply voltage, or in an IC having multiple power grid structures (e.g., one in each quadrant, etc.).


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