The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 29, 2009
Filed:
Feb. 28, 2007
Bernhard Laschinsky, Allentown, PA (US);
Neil C. Puthuff, Ladera Ranch, CA (US);
Francis H. Reiff, Manitou Springs, CO (US);
Million Woldesenbet, Annandale, NJ (US);
Bernhard Laschinsky, Allentown, PA (US);
Neil C. Puthuff, Ladera Ranch, CA (US);
Francis H. Reiff, Manitou Springs, CO (US);
Million Woldesenbet, Annandale, NJ (US);
Agere Systems Inc., Allentown, PA (US);
Abstract
An integrated circuit (IC) having a link layer that (1) simultaneously receives both hardware debug data from on-chip ASIC logic and software debug data from an on-chip programmable processor and (2) serializes the hardware and software debug data streams to generate one or more serialized debug data streams, e.g., containing both hardware and software debug data, for output to off-chip debug testing equipment to support debug testing of both the ASIC logic and the programmable processor. Cross triggering can be implemented on-chip to support simultaneous display of correlated hardware and software debug information on appropriate monitors. The present invention supports debug testing using external debug testing equipment that does not require a hardware logic analyzer.