The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 29, 2009
Filed:
Mar. 14, 2007
Hideaki Konishi, Kawasaki, JP;
Ryuji Shimizu, Kawasaki, JP;
Masayasu Hojo, Kawasaki, JP;
Haruhiko Abe, Kawasaki, JP;
Satoshi Masuda, Kawasaki, JP;
Naofumi Kobayashi, Kawasaki, JP;
Hideaki Konishi, Kawasaki, JP;
Ryuji Shimizu, Kawasaki, JP;
Masayasu Hojo, Kawasaki, JP;
Haruhiko Abe, Kawasaki, JP;
Satoshi Masuda, Kawasaki, JP;
Naofumi Kobayashi, Kawasaki, JP;
Fujitsu Microelectronics Limited, Tokyo, JP;
Abstract
In a delay failure test circuit, a delay failure test between two clock domains among a plurality of clock domains having different operation clock rates is performed. The delay failure test circuit inputs, to a first clock domain, a clock signal having only a launch edge for transferring data from the first clock domain to a second clock domain, and to input, to the second clock domain, a clock signal having only a capture edge for capturing the data.