The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2009

Filed:

Aug. 01, 2007
Applicants:

Jang-won Moon, Anyang-si, KR;

Young-hyun Jun, Seoul, KR;

Jong-hyoung Lim, Gyeonggi-do, KR;

Inventors:

Jang-won Moon, Anyang-si, KR;

Young-hyun Jun, Seoul, KR;

Jong-hyoung Lim, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided is a semiconductor memory device and method that can control internal supply voltages independently. The semiconductor memory device includes a memory cell array, a reference voltage generating unit, an internal reference voltage generating unit, and an internal supply voltage generating unit. The reference voltage generating unit outputs a reference voltage in response to an external voltage. The internal reference voltage generating unit converts the reference voltage into a plurality of internal reference voltages, and outputs the plurality of internal reference voltages. The internal supply voltage generating unit converts the plurality of internal reference voltages into a plurality of internal supply voltages, and outputs the plurality of internal supply voltages. A first internal reference voltage is used to generate a first internal supply voltage and a second internal reference voltage is used to generate a second internal supply voltage.


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