The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2009

Filed:

Apr. 25, 2008
Applicants:

David H. Shen, San Jose, CA (US);

Ann P. Shen, Saratoga, CA (US);

Axel Schuur, Mountain View, CA (US);

Inventors:

David H. Shen, San Jose, CA (US);

Ann P. Shen, Saratoga, CA (US);

Axel Schuur, Mountain View, CA (US);

Assignee:

NanoAmp Mobile, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/10 (2006.01); H03L 7/18 (2006.01); H04B 1/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Implementations feature systems and techniques for phase-locked loops (PLLs). In some aspects, implementations feature a system that has a PLL circuit including an oscillator and programmable reference frequency divider circuit or a programmable feedback frequency divider circuit. The PLL includes a control circuit to reduce a time required for a PLL settling time by programming a division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit to target the oscillator to operate outside of a system operating frequency range of the oscillator during start-up of PLL operations. The control circuit can program another division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit after stabilization of the variable oscillator.


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