The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2009

Filed:

Mar. 28, 2007
Applicants:

Roland Irsigler, Munich, DE;

Steve Wood, Munich, DE;

Hermann Ruckerbauer, Moos, DE;

Richard Johannes Luyken, Munich, DE;

Carsten Niepelt, Dietramszell, DE;

Inventors:

Roland Irsigler, Munich, DE;

Steve Wood, Munich, DE;

Hermann Ruckerbauer, Moos, DE;

Richard Johannes Luyken, Munich, DE;

Carsten Niepelt, Dietramszell, DE;

Assignee:

Qimonda AG, Munich, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device having a stacked arrangement of a substrate and a first chip and a second chip is disclosed. In one embodiment, the first chip is arranged with a lower face on an upper face of the substrate; the second chip with a lower face on an upper face of the first chip, whereby a partial area of the upper face of the first chip that is adjacent to an edge of the first chip is uncovered by the second chip; a fifth wire contact pad is arranged on the uncovered area of the upper face of the first chip; a first bonding wire is arranged that is connected with a first wire contact pad of the substrate and the fifth wire contact pad of the first chip.


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