The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 29, 2009
Filed:
Jan. 25, 2006
Hugh Sungki O, Fremont, CA (US);
Chih-ching Shih, Pleasanton, CA (US);
Cheng-hsiung Huang, Cupertino, CA (US);
Yow-juang Bill Liu, San Jose, CA (US);
Hugh Sungki O, Fremont, CA (US);
Chih-Ching Shih, Pleasanton, CA (US);
Cheng-Hsiung Huang, Cupertino, CA (US);
Yow-Juang Bill Liu, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
An ESD protection structure includes, in part, a NMOS transistor having a source and drain in a well in a substrate and a gate on the substrate with the source and drain being connected between ground and a series diode, and the gate being connected to ground. The structure further includes a diode having a cathode connected to the input pad and an anode connected to the well so that the diode is reverse-biased in the event of a positive voltage ESD event on the input pad. As a result, in a positive voltage ESD event, the avalanche effect rapidly injects current into the substrate and therefore into the base of the parasitic bipolar transistor so as to trigger the transistor into conduction and discharge the ESD pulse. Alternatively, the diode is a Zener diode and the current is generated by the Zener effect. A complementary structure provides protection against a negative ESD pulse.