The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 22, 2009
Filed:
Nov. 28, 2007
Katsuaki Natori, Yokohama, JP;
Katsuyuki Sekine, Yokohama, JP;
Daisuke Nishida, Yokohama, JP;
Ryota Fujitsuka, Yokohama, JP;
Masayuki Tanaka, Yokohama, JP;
Kazuaki Nakajima, Tokyo, JP;
Yoshio Ozawa, Yokohama, JP;
Akihito Yamamoto, Naka-gun, JP;
Katsuaki Natori, Yokohama, JP;
Katsuyuki Sekine, Yokohama, JP;
Daisuke Nishida, Yokohama, JP;
Ryota Fujitsuka, Yokohama, JP;
Masayuki Tanaka, Yokohama, JP;
Kazuaki Nakajima, Tokyo, JP;
Yoshio Ozawa, Yokohama, JP;
Akihito Yamamoto, Naka-gun, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A semiconductor device includes a semiconductor substrate, and a memory cell array provided on the semiconductor substrate and including a plurality of memory cells arranged on the semiconductor substrate, each of the plurality of the memory cells including a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a second insulating film provided on the charge storage layer, and a control electrode containing metal or metal silicide provided on the charge storage layer via the second insulating film, wherein a corner of a lower part of the control electrode includes semiconductor and fails to contain the metal or the metal silicide in a channel width direction view of the memory cell.