The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 22, 2009
Filed:
Apr. 13, 2007
Yoshio Ozawa, Yokohama, JP;
Akihito Yamamoto, Naka-gun, JP;
Masayuki Tanaka, Yokohama, JP;
Katsuaki Natori, Yokohama, JP;
Katsuyuki Sekine, Yokohama, JP;
Daisuke Nishida, Yokohama, JP;
Ryota Fujitsuka, Yokohama, JP;
Yoshio Ozawa, Yokohama, JP;
Akihito Yamamoto, Naka-gun, JP;
Masayuki Tanaka, Yokohama, JP;
Katsuaki Natori, Yokohama, JP;
Katsuyuki Sekine, Yokohama, JP;
Daisuke Nishida, Yokohama, JP;
Ryota Fujitsuka, Yokohama, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A semiconductor device includes a semiconductor substrate, a plurality of nonvolatile memory cells provided on the semiconductor substrate, each of the plurality of nonvolatile memory cells comprising a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a control gate electrode provided above the charge storage layer, a second insulating film provided between the control gate electrode and the charge storage layer, the second insulating film between adjacent charge storage layers including a first region having permittivity lower than that of the second insulating film on a top surface of the charge storage layer in a cross-section view of a channel width direction of the nonvolatile memory cell, and the first region having composition differing from that of the second insulating film on the top surface of the charge storage layer.