The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 15, 2009
Filed:
May. 12, 2005
Sankaranarayanan Parameswaran, Karnataka, IN;
Sriram Sethuraman, Karnataka, IN;
Manish Singhal, Karnataka, IN;
Dileep Kumar Tamia, Karnataka, IN;
Dinesh Kumar, Karnataka, IN;
Aditya Kulkarni, Karnataka, IN;
Murali Babu Muthukrishnan, Karnataka, IN;
Sankaranarayanan Parameswaran, Karnataka, IN;
Sriram Sethuraman, Karnataka, IN;
Manish Singhal, Karnataka, IN;
Dileep Kumar Tamia, Karnataka, IN;
Dinesh Kumar, Karnataka, IN;
Aditya Kulkarni, Karnataka, IN;
Murali Babu Muthukrishnan, Karnataka, IN;
Ittiam Systems (P) Ltd., Bangalore, Karnataka, IN;
Abstract
A method for designing a multi-threaded processing operation that includes, e.g., multimedia encoding/decoding, uses an architecture having multiple processors and optional hardware accelerators. The method includes the steps of: identifying a desired chronological sequence of processing stages for processing input data including identifying interdependencies of said processing stages; allotting each said processing sage to a processor; staggering the processing to accommodate the interdependencies; selecting a processing operation based on said allotting to arrive at a subset of possible pipelines that offer low average processing time; and, choosing one design pipeline from said subset to result in overall timing reduction to complete said processing operation. The invention provides a multi-threaded processing pipeline that is applicable in a System-on-Chip (SoC) using a DSP and shared resources such as DMA controller and on-chip memory, for increasing the throughput. The invention also provides an article which is programmed to execute the method.