Digital loop circuit for programmable logic device

Abstract

A digital loop circuit—i.e., a phase-locked loop ('PLL') or delay-locked loop ('DLL')—having a simplified digital loop filter, is particularly well-suited for a programmable logic device (“PLD”). The loop filter may be a memory (e.g., a shift register) which counts the early/late or up/down signals from a phase detector or phase-frequency detector (“error detector”) and outputs a signal when the count exceeds a threshold. Separate integral and proportional paths of the loop may include chained shift registers, with each outputting a signal only when the previous shift register overflows into it. A digital error detector may respond nonlinearly, with outputs of different bit widths, to different amounts of phase or frequency error.