The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 15, 2009
Filed:
May. 15, 2007
Rambod Jacoby, San Jose, CA (US);
Rambod Jacoby, San Jose, CA (US);
NVIDIA Corporation, Santa Clara, CA (US);
Abstract
One embodiment of the present invention sets forth a system and a method for testing the worst-case transients in the output voltage produced by a switching-mode power supply (SMPS). The system includes an SMPS and a dynamic load generator (DLG). The SMPS converts the input voltage into the output voltage by using a top field-effect transistor (FET) and a bottom FET. The worst case transients occur when the load being provided to the SMPS is turned on or off at the same time the top FET is turned off. The DLG is configured to monitor the edge of the gate voltage of the top FET and to turn the load provided to the SMPS on or off when the edge of the gate voltage of the top FET is falling. Consequently, the disclosed system is able to test the worst-case transients in the output voltage produced by the SMPS in a manner that is more reliable than prior art approaches.