The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2009

Filed:

Mar. 07, 2006
Applicant:

Makoto Terui, Yamana, JP;

Inventor:

Makoto Terui, Yamana, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

When an integrated circuit is formed in a semiconductor wafer, the integrated circuit is formed only in the central part of each chip region. In a case where packaging other than a chip size package is made, only the central part in which the integrated circuit is formed is cut from the wafer. In a case where a chip size package is made, the chip region is cut from the wafer after forming the redistribution wiring and external terminals and so forth over the whole of the chip region. As a result, the design of the integrated circuit and part of the fabrication process thereof can be shared by a chip which is mounted in a chip size package and a chip which is mounted in another type of package.


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