Systems and methods for providing fixed-latency data access in a memory system having multi-level caches

Abstract

Systems and methods for bypassing lower level caches and enabling direct access to higher level caches in order to provide fixed data latency and increased amounts of immediately accessible storage. One embodiment comprises a memory system having multiple cache memories that have increasing data latencies and amounts of storage. In a first mode which is suitable to support a microprocessor mode of a dual-mode processor, each data access proceeds conventionally, with accesses to successively higher levels of cache memory. In a second mode which is suitable to support a DSP mode of the dual-mode processor, the memory system bypasses the lower level cache and directly accesses the higher level cache in order to achieve a fixed latency (with enough cache storage to be useful to operate the processor in a DSP mode.)