The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 2009
Filed:
Jul. 13, 2007
Sharmin Sadoughi, Menlo Park, CA (US);
Krishnaswamy Ramkumar, San Jose, CA (US);
Ravindra Kapre, San Jose, CA (US);
Igor Polishchuk, Fremont, CA (US);
Maroun Khoury, Hillsboro, OR (US);
Sharmin Sadoughi, Menlo Park, CA (US);
Krishnaswamy Ramkumar, San Jose, CA (US);
Ravindra Kapre, San Jose, CA (US);
Igor Polishchuk, Fremont, CA (US);
Maroun Khoury, Hillsboro, OR (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
In one embodiment, an integrated circuit includes a PMOS transistor having a gate stack comprising a P+ doped gate polysilicon layer and a nitrided gate oxide (NGOX) layer. The NGOX layer may be over a silicon substrate. The integrated circuit further includes an interconnect line formed over the transistor. The interconnect line includes a hydrogen getter material and may comprise a single material or stack of materials. The interconnect line advantageously getters hydrogen (e.g., Hor HO) that would otherwise be trapped in the NGOX layer/silicon substrate interface, thereby improving the negative bias temperature instability (NBTI) lifetime of the transistor.