The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 2009
Filed:
Apr. 15, 2005
Jung-hwan Kim, Gyeonggi-do, KR;
Hun-hyeoung Leam, Gyeonggi-do, KR;
Jai-dong Lee, Gyeonggi-do, KR;
Young-seok Kim, Seoul, KR;
Young-sub You, Gyeonggi-do, KR;
Ki-su NA, Gyeonggi-do, KR;
Woong Lee, Gyeonggi-do, KR;
Jung-Hwan Kim, Gyeonggi-do, KR;
Hun-Hyeoung Leam, Gyeonggi-do, KR;
Jai-Dong Lee, Gyeonggi-do, KR;
Young-Seok Kim, Seoul, KR;
Young-Sub You, Gyeonggi-do, KR;
Ki-Su Na, Gyeonggi-do, KR;
Woong Lee, Gyeonggi-do, KR;
Abstract
In a method of manufacturing a floating gate of a non-volatile semiconductor memory, a pattern is formed on a substrate to have an opening that exposes a portion of the substrate. A first preliminary polysilicon layer is formed on the pattern and the exposed portion of the substrate to substantially fill the opening. A first polysilicon layer is formed by partially etching the first preliminary polysilicon layer until a first void formed in the first preliminary polysilicon layer is exposed. A second polysilicon layer is formed on the first polysilicon layer.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile