The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 2009
Filed:
Oct. 04, 2005
Nathan P. Chelstrom, Cedar Park, TX (US);
Mack W. Riley, Austin, TX (US);
Shoji Sawamura, Austin, TX (US);
Nathan P. Chelstrom, Cedar Park, TX (US);
Mack W. Riley, Austin, TX (US);
Shoji Sawamura, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A clock control hierarchy is provided that is comprised of synchronous and asynchronous hold request signals that are used to start and stop functional units of a chip. Pervasive logic is provided that uses a synchronous 'chip hold' signal and asynchronous latch/functional unit hold signals to individually target functional units and latches that are to remain in a held state once the 'chip hold' state is released. With the present invention, a chip hold request is first activated followed by scannable latch and non-scannable latch hold requests being activated to identify which latches will be clocked or not clocked when the chip hold is released. Functional unit hold signals are activated to place certain ones of the functional units of the chip in a hold state. The chip hold request is deactivated and the chip operates with the selected functional units and latches being maintained in a held state.