The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 2009
Filed:
Apr. 17, 2007
Charles M. Branch, Dallas, TX (US);
Steven C. Bartling, Plano, TX (US);
Charles M. Branch, Dallas, TX (US);
Steven C. Bartling, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
Various systems and methods for implementing memory devices are disclosed. For example, some embodiments of the present invention provide sub-threshold memory devices that include a differential bit cell. Such a differential bit cell includes two PMOS transistors, two NMOS transistors, and two inverters. The source of the first PMOS transistor and the source of the second PMOS transistor are electrically coupled to a bit line input, and the source of the first NMOS transistor and the source of the second NMOS transistor are electrically coupled to the bit line input. The gate of the first NMOS transistor and the gate of the second NMOS transistor are electrically coupled to a word line input. The gate of the first PMOS transistor and the gate of the second PMOS transistor are electrically coupled to an inverted version of the word line input. The drain of the first PMOS transistor is electrically coupled to the drain of the first NMOS transistor, and the drain of the second PMOS transistor is electrically coupled to the drain of the second NMOS transistor. In addition, the drain of the first PMOS transistor is electrically coupled to the drain of the second PMOS transistor by the first inverter, and the drain of the second PMOS transistor is electrically coupled to the drain of the first PMOS transistor by the second inverter.