The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 2009
Filed:
Mar. 13, 2008
Applicant:
Srinath Krishnan, Campbell, CA (US);
Inventor:
Srinath Krishnan, Campbell, CA (US);
Assignee:
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/93 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce strain in the substrate.