The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2009

Filed:

Feb. 21, 2006
Applicants:

Charles H. Joyner, Sunnyvale, CA (US);

Mark J. Missey, San Jose, CA (US);

Radhakrishnan L. Nagarajan, Cupertino, CA (US);

Fred A. Kish, Jr., Palo Alto, CA (US);

Inventors:

Charles H. Joyner, Sunnyvale, CA (US);

Mark J. Missey, San Jose, CA (US);

Radhakrishnan L. Nagarajan, Cupertino, CA (US);

Fred A. Kish, Jr., Palo Alto, CA (US);

Assignee:

Infinera Corporation, Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for reducing insertion loss in a transition region between a plurality of input or output waveguides to a free space coupler region in a photonic integrated circuit (PIC) includes the steps of forming a passivation layer over the waveguides and region and forming the passivation overlayer such that it monotonically increases in thickness through the transition region to the free space coupler region.


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