The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 24, 2009
Filed:
Feb. 27, 2007
Jason R. Baumgartner, Austin, TX (US);
Tobias Gemmeke, Boeblingen, DE;
Nicolas Maeding, Holzgerlingen, DE;
Kai O. Weber, Boeblingen, DE;
Jason R. Baumgartner, Austin, TX (US);
Tobias Gemmeke, Boeblingen, DE;
Nicolas Maeding, Holzgerlingen, DE;
Kai O. Weber, Boeblingen, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for performing equivalence checking on logic circuit designs is disclosed. Within a composite netlist of an original version and a modified version of a logic circuit design, all level-sensitive sequential elements sensitized by a clock=0 are converted into buffers, and all level-sensitive sequential elements sensitized by a clock=1 are converted into level-sensitive registers. A subset of edge-sensitive sequential elements are selectively transformed into level-sensitive sequential elements by removing edge detection logic from the subset of the edge-sensitive sequential elements. A clock to the resulting sequential elements is then set to a logical '1' to verify the sequential equivalence of the transformed netlist.