The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2009

Filed:

Jun. 29, 2004
Applicants:

Kendal Mcnaught-davis Hess, Encinitas, CA (US);

Manjit S. Gill, San Diego, CA (US);

Donald Brian Eidson, San Diego, CA (US);

Chi-ping Nee, Santee, CA (US);

Mats Lindstrom, San Diego, CA (US);

Abraham Krieger, San Diego, CA (US);

Fred Harris, Lemon Grove, CA (US);

Inventors:

Kendal McNaught-Davis Hess, Encinitas, CA (US);

Manjit S. Gill, San Diego, CA (US);

Donald Brian Eidson, San Diego, CA (US);

Chi-Ping Nee, Santee, CA (US);

Mats Lindstrom, San Diego, CA (US);

Abraham Krieger, San Diego, CA (US);

Fred Harris, Lemon Grove, CA (US);

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04K 1/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

A simultaneous multiple channel receiver ('SMCR') for receiving a combined signal having a plurality of carrier signals, where each carrier signal in the plurality of carriers signals corresponds to a frequency channel, and in response, simultaneously producing a plurality of output data stream signals, is disclosed. The SMCR may include a down-converter front-end capable of receiving the combined signal, a plurality of digital signal processors, wherein each digital signal processor of the plurality of digital signal processors is capable of producing an output data stream signal of the plurality of output data stream signals, and a multi-band filter in signal communication with both the down-converter front-end and the plurality of digital signal processors.


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