The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2009

Filed:

Dec. 13, 2006
Applicants:

Michael Le, Laguna Niguel, CA (US);

Chun-ying Chen, Irvine, CA (US);

Wynstan Tong, Irvine, CA (US);

Kwang Young Kim, Irvine, CA (US);

Hui Pan, Irvine, CA (US);

Inventors:

Michael Le, Laguna Niguel, CA (US);

Chun-Ying Chen, Irvine, CA (US);

Wynstan Tong, Irvine, CA (US);

Kwang Young Kim, Irvine, CA (US);

Hui Pan, Irvine, CA (US);

Assignee:

Broadcom Corporation, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and apparatus to counter effects of an offset voltage by calibrating an analog-to-digital converter (ADC). A digital calibration loop minimizes the effects of offset voltage to improve ADC accuracy as well as provide a low-power, submicron-scale ADC. A calibration circuit senses an ADC output and adjusts a variable calibration voltage to counter the effects of the offset voltage. Reduction of the offset voltage effects increases the ADC accuracy.


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