The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 24, 2009
Filed:
Oct. 31, 2007
Applicants:
Ajay Bhatia, Santa Clara, CA (US);
Rajesh Khanna, Fremont, CA (US);
Inventors:
Ajay Bhatia, Santa Clara, CA (US);
Rajesh Khanna, Fremont, CA (US);
Assignee:
Sun Microsytems, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
A timing-constrained circuit (e.g., a self-timed circuit) of optimal performance is achieved by allowing the delay of the circuit to be changed dynamically as a function of operating conditions (e.g., operating voltages or temperatures). The delay of timing signals in the timing-constrained circuit for a given operating condition may be selected to have the minimum margin for that operating condition among the available delays to maximize performance over the entire dynamic range of operating conditions.