The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 24, 2009
Filed:
Apr. 17, 2008
Ramaprasath Vilangudipitchai, Dallas, TX (US);
Sumanth Katte Gururajarao, Dallas, TX (US);
Hugh T. Mair, Fairview, TX (US);
Alice Wang, Allen, TX (US);
Uming U. Ko, Plano, TX (US);
Sushma Honnavara-prasad, Dallas, TX (US);
Ramaprasath Vilangudipitchai, Dallas, TX (US);
Sumanth Katte Gururajarao, Dallas, TX (US);
Hugh T. Mair, Fairview, TX (US);
Alice Wang, Allen, TX (US);
Uming U. Ko, Plano, TX (US);
Sushma Honnavara-Prasad, Dallas, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving mode (APSM) to reduce power. The OLS operating in the APSM provides a level shifter output having a configurable voltage, thereby providing output isolation. A change in an operating mode of the MSFF between an active mode and the APSM is independent of a retention (RET) mode input.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile