The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2009

Filed:

May. 28, 2008
Applicants:

Chooi Pei Lim, Penang, MY;

Siang Poh Loh, Penang, MY;

Hong Ming Siew, Penang, MY;

Inventors:

Chooi Pei Lim, Penang, MY;

Siang Poh Loh, Penang, MY;

Hong Ming Siew, Penang, MY;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A structured ASIC device includes highly flexible clock signal routing to peripheral IO circuitry of the device. A plurality of peripheral IO circuits are divided into subpluralities of adjacent ones of those circuits. Each subplurality has associated clock signal routing that is mask-programmable to supply any of a plurality of clock signals to any of the IO circuits in the subplurality. Core circuitry of the structured ASIC includes clock signal distribution circuitry, and that distribution circuitry can supply (via buffers associated with each subplurality) the same plurality of clock signals to the routing circuitry associated with all of the subpluralities.


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