Methods for detecting resistive bridging faults at configuration random-access memory output nodes

Abstract

Integrated circuits such as programmable logic device integrated circuits have configuration random-access memory elements. The configuration random-access memory elements are tested to determine whether any of the elements have resistive bridging faults at their outputs. During testing, a pattern of test configuration data is loaded into the configuration random-access memory elements. The programmable logic device is placed in user mode to clear programmable logic registers on the device. The configuration random-access memory elements are sensitized to the presence of resistive bridging faults by performing read operations. After sensitizing the configuration random-access memory elements, a tester applies test vectors to the programmable logic of the programmable logic device. As the test vectors are applied, the tester observes whether the programmable logic of the device is performing properly or has been affected by the presence of a resistive bridging fault.