The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2009

Filed:

Oct. 18, 2005
Applicants:

Takashi Koba, Kodaira, JP;

Naoyuki Anan, Ome, JP;

Mikiko Sakai, Ome, JP;

Seryung Park, Akishima, JP;

Keiichi Higeta, Hamura, JP;

Inventors:

Takashi Koba, Kodaira, JP;

Naoyuki Anan, Ome, JP;

Mikiko Sakai, Ome, JP;

Seryung Park, Akishima, JP;

Keiichi Higeta, Hamura, JP;

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A circuit system is provided capable of improving the throughput thereof by eliminating the operational constraint that if the operating frequency of a content addressable memory is lower than the operating frequency of a system LSI, two system clocks should be provided, or the higher frequency should be synchronized with the slower system clock. A clock control circuit () for down-converting an internal clock (Φ) of a LSI () is provided, and a control signal whose frequency is made lower is used to operate a content addressable memory circuit ().


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