Serial interface circuit for data transfer

Abstract

A serial interface circuit includes a first circuit disposed in the core portion and connected to the CPU, and a second circuit disposed in the peripheral circuit and connected to the peripheral registers and the first circuit; the first circuit including mirror registers, shift registers, in the write operation, serially outputting write data to the second circuit, and in the read operation, serially receiving read data supplied from the second circuit, and a first control block, in the read operation, generating a timing signal for writing the read data held in the shift registers into the corresponding mirror registers; the second circuit including shift registers and a second control block generating a second timing signal for either writing the write data held in the second shift register into the corresponding peripheral register or outputting data held in the peripheral register to the second shift register.