The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2009

Filed:

Aug. 03, 2005
Applicant:

Hitanshu Dewan, Delhi, IN;

Inventor:

Hitanshu Dewan, Delhi, IN;

Assignee:

STMicroelectronics Pvt. Ltd., Uttar Pradesh, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

An improved logic entity with two outputs for efficient adder and other macro implementations providing fast response with reduced area requirements, comprising a first lookup table for generating a first output for the carry out value for a carry-in of zero and a second output for the sum value for a carry-in of one; a second lookup table for generating a first output for the carry out value for a carry-in of one and a second output for the sum value for a carry-in of zero; a first multiplexer is connected to a first input from the first output of the first lookup table and a second input from the first output of the second lookup table; a second multiplexer is connected to a first input from the second output of the first lookup table and a second input from the second output of the second lookup table; thereby, getting two output taps for sum and carry implementation.


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