The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2009

Filed:

Feb. 16, 2005
Applicants:

Jeong-won Lee, Sungnam-si, KR;

Jung-hyun Lee, Seoul, KR;

Jae-wook Lee, Osan-si, KR;

Jung-eun Lee, Sungnam-si, KR;

Konakov Maxim, Suwon-si, KR;

Inventors:

Jeong-won Lee, Sungnam-si, KR;

Jung-hyun Lee, Seoul, KR;

Jae-wook Lee, Osan-si, KR;

Jung-eun Lee, Sungnam-si, KR;

Konakov Maxim, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B 3/06 (2006.01); G11B 20/10 (2006.01); G11B 20/14 (2006.01); G11B 20/18 (2006.01); G11B 5/09 (2006.01);
U.S. Cl.
CPC ...
Abstract

A high-speed mixed analog/digital PRML data detection and clock recovery apparatus and method. The high-speed mixed analog/digital PRML data detection and clock recovery apparatus includes a variable gain amplifier, an analog equalizer, an analog-to-digital (A/D) converter, a DC offset remover, a level error detector, a Viterbi decoder, and an adaptive digital controller. The adaptive digital controller separately stores the level error values by predetermined frequencies, calculates predetermined coefficient values by each frequency component based on the level error values, and D/A-converts and applies the calculated predetermined coefficient values to the variable gain amplifier and the analog equalizer.


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