The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 10, 2009
Filed:
Apr. 24, 2008
Masayuki Hirayama, Tachikawa, JP;
Masami Hasegawa, Ome, JP;
Michitaro Kanamitsu, Ome, JP;
Yayoi Hayashi, Akishima, JP;
Naoyuki Anan, Hino, JP;
Masayuki Hirayama, Tachikawa, JP;
Masami Hasegawa, Ome, JP;
Michitaro Kanamitsu, Ome, JP;
Yayoi Hayashi, Akishima, JP;
Naoyuki Anan, Hino, JP;
Hitachi ULSI Systems Co., Ltd, Tokyo, JP;
Abstract
A semiconductor device of the present invention has a memory cell array having plural CMOS static memory cells provided at intersecting portions of plural word lines and plural complementary bit lines. In the memory cell array, a switch MOSFET which is in an OFF state in a first operation mode and in an ON state in a second operation mode different from the first operation mode and first-conductivity-type and second-conductivity-type MOSFETs having a diode configuration are provided in parallel between a first source line to which sources of first-conductivity-type MOSFETs constituting first and second CMOS inverter circuits constituting the plural static memory cells are connected and a first power supply line corresponding to the first source line. A second source line to which sources of the second conductivity-type MOSFETs constituting the first and second CMOS inverter circuits are connected is connected to the second power supply line corresponding thereto.