The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 10, 2009
Filed:
Jun. 15, 2006
Mitsuhiro Yamamura, Suwa, JP;
Mitsuhiro Yamamura, Suwa, JP;
Seiko Epson Corporation, , JP;
Abstract
A ferroelectric memory array includes a plurality of bit lines; a plurality of memory cells connected to the bit lines and storing predetermined data; and a plurality of sense amplifiers provided in correspondence with the bit lines and amplifying data that are read out from the memory cells. The sense amplifiers each include a first n-MOS transistor, a first voltage being supplied to a source of the first n-MOS transistor; a first precharge unit precharging a drain of the first n-MOS transistor to a second voltage, which is a positive voltage that is higher than the first voltage; a transistor control unit that lowers the drain voltage that has been precharged to the second voltage by controlling a resistance between the source and the drain of the first n-MOS transistor in accordance with a voltage on a corresponding bit line, when data stored in the memory cells is read out to that bit line; and a voltage control unit that lowers the voltage of the bit line in accordance with the lowering of the voltage of the drain.