The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 10, 2009
Filed:
Sep. 12, 2007
Sibaprasad Chakrabarti, Torrance, CA (US);
Silva Hiti, Redondo Beach, CA (US);
George John, Cerritos, CA (US);
Gregory S. Smith, Woodland Hills, CA (US);
Milun Perisic, Torrance, CA (US);
Gholamreza Esmaili, Torrance, CA (US);
Sibaprasad Chakrabarti, Torrance, CA (US);
Silva Hiti, Redondo Beach, CA (US);
George John, Cerritos, CA (US);
Gregory S. Smith, Woodland Hills, CA (US);
Milun Perisic, Torrance, CA (US);
Gholamreza Esmaili, Torrance, CA (US);
GM Global Technology Operations, Inc., Detroit, MI (US);
Abstract
An inverter circuit couples a DC voltage source having a primary side and a reference side to an electric motor or other AC machine having multiple electrical phases. An inverter circuit includes switches, diodes and a controller. For each of the electrical phases, a first switch couples the electrical phase to the primary side of the DC voltage source and a second switch couples the electrical phase with the reference side of the DC voltage source. For each of the first and second switches, an associated anti-parallel diode is configured to provide an electrical path when the switch associated with the diode is inactive. The controller is coupled to the switching inputs of each of the first and second switches and is configured to provide a control signal thereto, wherein the control signal provided to each switch comprises, in a low frequency mode, a first portion and a second portion, wherein the first portion comprises a first pulse width modulation scheme and the second portion comprises a second pulse width modulation scheme different from the first modulation scheme.