The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2009

Filed:

Oct. 06, 2005
Applicant:

Subhas Bothra, Fremont, CA (US);

Inventor:

Subhas Bothra, Fremont, CA (US);

Assignee:

Broadcom Corporation, Irvine, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Embodiments of the present invention provide a system and method with which to implement metal fill during design using tools such as a place and route tools or layout tools. Unlike prior known solutions where metal fill was performed after design and layout, performing metal fill during layout with a uniform pattern of conductive traces sized and spaced according to the design rules of the device to be fabricated resulting in more planning and design. Dividing the conductive traces into active and inactive segments during the design and layout identifies potentially negative impacts on critical or sensitive device elements within the device during design and layout. Previously, metal fill was implemented after design and layout and often resulted in negative impacts not previously accounted for during IC design. Embodiments of the present invention reduce degradation, seen in other devices where metal fill is incorporated after design and layout. Additionally, because the physical characteristics of inactive metal fill segments are considered during design and layout of the ICs.


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