The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2009

Filed:

Feb. 15, 2007
Applicants:

Hiroyasu Nishimura, Hachioji, JP;

Tomohiro Suzuki, Nishitokyo, JP;

Yuji Tamura, Hachioji, JP;

Tetsuya Ishikawa, Hachioji, JP;

Tomoya Ogawa, Hachioji, JP;

Fumikage Uchida, Asaka, JP;

Nao Moromizato, Hino, JP;

Masayuki Yasukaga, Hachioji, JP;

Munetoshi Eguchi, Hachioji, JP;

Inventors:

Hiroyasu Nishimura, Hachioji, JP;

Tomohiro Suzuki, Nishitokyo, JP;

Yuji Tamura, Hachioji, JP;

Tetsuya Ishikawa, Hachioji, JP;

Tomoya Ogawa, Hachioji, JP;

Fumikage Uchida, Asaka, JP;

Nao Moromizato, Hino, JP;

Masayuki Yasukaga, Hachioji, JP;

Munetoshi Eguchi, Hachioji, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory administrating method of administrating a memory divided into plural regions each of which consists of consecutive memory addresses, where the method includes the steps of: providing each region of the plural regions with usage information; and when releasing a release target region currently in use, determining usage of the release target region based on the usage information of at least one of neighboring regions positioned before and after the release target region.


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