The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2009

Filed:

May. 15, 2007
Applicants:

Masatake Hangai, Tokyo, JP;

Yukinobu Tarui, Tokyo, JP;

Tamotsu Nishino, Tokyo, JP;

Yoshitsugu Yamamoto, Tokyo, JP;

Moriyasu Miyazaki, Tokyo, JP;

Yoji Isota, Tokyo, JP;

Inventors:

Masatake Hangai, Tokyo, JP;

Yukinobu Tarui, Tokyo, JP;

Tamotsu Nishino, Tokyo, JP;

Yoshitsugu Yamamoto, Tokyo, JP;

Moriyasu Miyazaki, Tokyo, JP;

Yoji Isota, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01P 1/10 (2006.01); H01P 1/15 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a high-frequency switch including: a first switching element connected between a first input/output terminal and a second input/output terminal; a second switching element connected between the second input/output terminal and the first switching element; a high-frequency line provided between the first input/output terminal, the first switching element, and a third input/output terminal; and a third switching element connected between the third input/output terminal, the high-frequency line, and a ground. By connecting the first switching element, the second switching element, the high-frequency line, and the third switching element, because there exists no FET through which a large current flows when a state between the first input/output terminal and the third input/output terminal is set to a transmission state which requires high power handling capability, there is no need to use an FET having a large gate width, which is effective in reducing a loss of the switch.


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