The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2009
Filed:
May. 19, 2008
David James Megaw, Tucson, AZ (US);
David James Megaw, Tucson, AZ (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A circuit for providing a self-stabilizing, differential load circuit with well controlled complex impedance to an amplifier is described. According to an embodiment, two pairs of transistors in a cross-coupled configuration, a degeneration resistor for each transistor, and parasitic capacitance cancelation capacitors provide a self-stabilizing, differential load. Small signal analysis of the circuit illustrates an impedance of the load circuit to be substantially equal to a combination of impedance values with substantially little dependence on transconductances and incremental resistances of the transistors over an extended frequency range. By employing well matched resistors, impedance of the load to the amplifier can be controlled and common mode feedback loops avoided, because a current source is not employed as a load. The use of parasitic capacitance cancelation capacitors can substantially increase the bandwidth of the amplifier. Furthermore, with transistors, low voltage headroom may be increased and integrated circuit area decreased.