The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2009
Filed:
Dec. 18, 2007
James E. Boyle, Saratoga, CA (US);
Reese Reynolds, Los Gatos, CA (US);
Raanan Y. Zehavi, Sunnyvale, CA (US);
Robert W. Mytton, Salem, OR (US);
Doris Mytton, Legal Representative, Salem, OR (US);
Tom L. Cadwell, Los Altos, CA (US);
James E. Boyle, Saratoga, CA (US);
Reese Reynolds, Los Gatos, CA (US);
Raanan Y. Zehavi, Sunnyvale, CA (US);
Robert W. Mytton, Salem, OR (US);
Doris Mytton, legal representative, Salem, OR (US);
Tom L. Cadwell, Los Altos, CA (US);
Integrated Materials, Inc., Sunnyvale, CA (US);
Abstract
Non-production wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. They may have thicknesses of 0.725 to 2 mm and be roughened on both sides. Nitride may be grown on the non-production wafers to a thickness of over 2 μm without flaking. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. Both sides are ground to introduce sub-surface damage and then oxidized and etch cleaned. An all-silicon hot zone of a thermal furnace, for example, depositing a nitride layer, may include a silicon support tower placed within a silicon liner and supporting the polysilicon non-production wafers with silicon injector tube providing processing gas within the liner.