The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 27, 2009
Filed:
Nov. 01, 2006
Aaron Matthew Volz, Fort Collins, CO (US);
Suzette Denise Vandivier, Fort Collins, CO (US);
Jeffrey Andrew Slavick, Fort Collins, CO (US);
Aaron Matthew Volz, Fort Collins, CO (US);
Suzette Denise Vandivier, Fort Collins, CO (US);
Jeffrey Andrew Slavick, Fort Collins, CO (US);
Avago Technologies General IP (Singapore) Pte. Ltd., Singapore, SG;
Abstract
An application specific integrated circuit (ASIC) uses a dedicated interface between core logic and an independent Serializer/De-serializer bus (SBus) to provide SBus capabilities to the core logic. In addition to the dedicated interface, the ASIC includes a controller responsive to a set of signals and a plurality of receivers distributed about the SBus. Each of the receivers is responsive to a set of commands that can be reused to test logic and support functions across each revision of the ASIC as well as to test separate ASICs with similar arrangements of support functions without requiring the generation of a distinct scan vector to test the ASIC. Additional interfaces, such as an I.E.E.E. 1149.1 interface, further extend SBus capabilities to external test equipment.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile