The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2009

Filed:

Mar. 28, 2006
Applicants:

Masatoshi Kokubun, Kasugai, JP;

Katsuyuki Yasukouti, Kasugai, JP;

Takashi Matsumoto, Kasugai, JP;

Inventors:

Masatoshi Kokubun, Kasugai, JP;

Katsuyuki Yasukouti, Kasugai, JP;

Takashi Matsumoto, Kasugai, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05F 1/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

A DC-DC converter that suppresses increase in area and obtains high conversion efficiency irrespective of the output current. A controller controls a first output transistor and a second output transistor in a PWM operation mode or a linear operation mode based on output voltage of the DC-DC converter. The controller operates the DC-DC converter as a switching regulator that activates and inactivates the first output transistor and the second output transistor in a complementary manner during the PWM operation mode. The controller operates the DC-DC converter as a linear regulator that inactivates the second output transistor and controls the ON-resistance value of the first output transistor to perform linear operation with the first output transistor during the linear operation mode.


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