The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 27, 2009
Filed:
Feb. 06, 2007
Byung-kwan You, Gyeonggi-do, KR;
Jun-eui Song, Gyeonggi-do, KR;
Gyeong-hee Kim, Gyeonggi-do, KR;
Hee-jueng Lee, Gyeonggi-do, KR;
Byung-Kwan You, Gyeonggi-do, KR;
Jun-Eui Song, Gyeonggi-do, KR;
Gyeong-Hee Kim, Gyeonggi-do, KR;
Hee-Jueng Lee, Gyeonggi-do, KR;
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Abstract
Provided is a method of forming a semiconductor device. A tunnel insulating layer is formed on a substrate having a cell region and a low voltage region. First and second charge storage gate patterns (e.g., floating gate patterns) are formed on the tunnel insulating layers of the cell and low voltage region, respectively. A blocking insulating layer and a control gate conductive layer are formed on the substrate in sequence. The control gate conductive layer, the blocking insulating layer, the second floating gate pattern and the tunnel insulating layer of the low voltage region are removed to expose the substrate of the low voltage region. The low-voltage gate insulating layer is formed on the exposed substrate. A low-voltage gate conductive pattern is formed on the low-voltage gate insulating layer.