The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2009

Filed:

Oct. 18, 2007
Applicants:

Yasuyuki Baba, Yokohama, JP;

Susumu Yoshikawa, Yokohama, JP;

Inventors:

Yasuyuki Baba, Yokohama, JP;

Susumu Yoshikawa, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/82 (2006.01);
U.S. Cl.
CPC ...
Abstract

A manufacturing method of a semiconductor memory device for manufacturing a first semiconductor device and a second semiconductor device wherein a cell array ratio is smaller than that of the first semiconductor device, said manufacturing method has forming the height of first element-isolating insulating films of first memory cell array region of said first semiconductor device so as to be a predetermined height, by performing etching treatment under predetermined conditions using a first etching mask having a first opening for exposing the entirety of said first memory cell array region, and forming the height of second element-isolating insulating films of second memory cell array region and part of peripheral circuit region of said second semiconductor device so as to be the predetermined height, by performing etching treatment under said predetermined conditions using a second etching mask having a second opening for exposing the entirety of said second memory cell array region and a third opening for exposing part of said peripheral circuit region.


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