The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7607116 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 20, 2009

Filed:

Dec. 27, 2007
Applicant:

Soon-wan Kwon, Gwangju-si, KR;

Inventor:

Soon-Wan Kwon, Gwangju-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for performing verification on a Transaction Level (TL) model having at least two abstraction levels in simulation modeling for design of a System-on-Chip (SoC). The TL model verification method includes acquiring first request information and first response information; acquiring second request information and second response information; dividing the first and second request information and the first and second response information; comparing the divided first and second request information and comparing the divided first and second response information; and verifying a modeling result on the TL model depending on the comparison results.


Find Patent Forward Citations

Kwon, Soon-Wan. (2009). Method and apparatus for verifying system-on-chip model (U.S. Patent No. 7607116). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7607116

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